1. Field of the Invention
The present invention relates to the formation of an insulating region between conducting structures in a semiconductor circuit.
2. Description of the Related Art
Many highly integrated semiconductor circuits utilize multilevel wiring line structures for interconnecting regions within devices and for interconnecting one or more devices within the integrated circuits. In forming such structures, it is conventional to provide first or lower level wiring lines or interconnect structures and then to form a second level wiring line in contact with the first level wiring lines or interconnect structures. A first level interconnect might be formed in contact with a doped region within the substrate of an integrated circuit device. Alternately, a first level interconnect might be formed to a polysilicon or metal wiring line that is in contact with one or more device structures in or on the substrate of the integrated circuit device. One or more interconnections are typically formed between the first level wiring line or interconnect and other portions of the integrated circuit device or to structures external to the integrated circuit device. This is accomplished, in part, through the second level of wiring lines.
Intermetal dielectric materials are provided between adjacent wiring lines within layers and between wiring lines on different levels. The dielectric materials are used to fill the gaps between adjacent wiring lines so that subsequent layers of materials deposited over the wiring lines do not extend between the wiring lines. Because the dielectric materials are generally left in place in the completed integrated circuit device, it is desirable for the dielectric materials to have certain characteristics. It is desirable that the dielectric material be highly insulative, provide significant levels of passivation to the surface of the typical metal wiring lines covered by the dielectric materials, and provide a moisture barrier to protect the wiring lines from the atmosphere through the life of the integrated circuit device. Other requirements for the dielectric materials provided between the wiring lines of the integrated circuit device relate to the performance of the integrated circuit device. Adjacent wiring lines couple to each other both capacitively and inductively through the dielectric materials that separate the wiring lines. Excessive levels of coupling between adjacent wiring lines slows the transmission of signals by the wiring lines, slowing circuit performance. As such, various efforts have been made to limit the dielectric constant of the dielectric materials that separate adjacent wiring lines.
As devices are scaled to smaller geometries, the gaps between wiring lines become smaller and it becomes ever more important to reduce the dielectric constant of the dielectric materials used to fill the gaps between wiring lines. This is particularly true for modern integrated circuit devices which emphasize not only closer spacings between wiring lines but also higher operating speeds so that there is a reduced margin for the slowing produced by excessive levels of capacitive and inductive coupling. Thus, modern integrated circuit devices need reduced dielectric constants to obtain the desirable reduced levels of capacitive and inductive coupling between adjacent wiring lines. One strategy for reducing the dielectric constant of the materials has been to replace conventional dielectric materials with new material having comparatively low dielectric constants, including fluorinated oxides and fluorinated carbon films. These materials do not yet provide an acceptable alternative to more conventional dielectric materials because of processing difficulties and unreliability. A different strategy that has been attempted has been to incorporate air-filled gaps or spaces within the dielectric materials that separate the wiring lines. The appeal of using air as a dielectric material between dielectric lines is that air closely approaches the theoretical minimum dielectric constant for a dielectric material. Air-filled gaps also have not been acceptably implemented in modem integrated circuits, particularly since use of air-filled gaps tend to reduce the reliability of integrated circuits in which they are incorporated and reduce the yields from processes subsequent to the formation of air-filled gaps.
Dielectric layers for wiring line isolation are often formed by chemical vapor deposition (CVD) processes, which deposit a material onto a surface by transporting certain gaseous precursors to the surface and causing the precursors to react at the surface. Common CVD methods are atmospheric-pressure CVD (APCVD), low-pressure CVD (LPCVD) and plasma enhanced CVD (PECVD). High quality APCVD and PLCVD oxides may be deposited at high temperatures (650-850.degree. C.), but such temperatures are generally not compatible with preferred wiring line materials such as aluminum. Lower temperature APCVD and LPCVD processes yield oxides that are porous and water absorbing and that may be poorly suited to use as intermetal dielectrics. Acceptable oxides for gap-filling have been formed using PECVD processes, which use a plasma to impart additional energy to the reactant gases. The additional energy supplied by the plasma enables PECVD processes to be carried out at lower temperatures (approximately 400.degree. C. and less) than APCVD or LPCVD processes.
The most common dielectric material deposited for metal line isolation is silicon dioxide. It would be desirable to utilize materials having a lower dielectric constant than that of silicon dioxide to reduce the capacitive coupling between adjacent wiring lines and to enhance circuit performance.